RZSLASHG2LC datasheet(47/74 Pages) RENESAS

47 / 74 page

RZ/G2L Group, RZ/G2LC Group

3. Electrical Characteristics

R01DS0484EJ0110

Rev.1.10

Page 47 of 74

May 30, 2025

Table 3.36

SPI Multi I/O Bus Conttoller Access Timing (2/2)

1.8 V

3.3 V

(Serial flash/octal-SPI

flash/hyper flash

connected)

(Serial flash connected)

Item

Symbol

Min.

Max.

Min.

Max.

Unit

Figures

Data output

buffer off time

SDR

tBOFF

―

2.0

―

3.0

Figure 3.29

DDR

―

2.0

―

3.0

Figure 3.29

AC differential crossing voltage

VOX

PVcc_SPI

× 0.4

PVcc_SPI

× 0.6

―

Figure 3.30

Note 1.

Output load: 15 pF/driving ability: 12 mA

Note 2.

QSPI0_SPCLK frequency: 100 MHz.

Note 3.

QSPI0_SPCLK frequency: 66 MHz

tSPBcyc

tSPBWL

tSPBWH

tSPBF

tSPBR

QSPI0_SPCLK

QSPI1_SPCLK

Output

Figure 3.26

Clock Timing

QSPI0_SSL

QSPI1_SSL

Output

QSPI0_SPCLK

QSPI1_SPCLK

Output

QSPI0_IO[0:3]

QSPI1_IO[0:3]

Input

QSPI0_IO[0:3]

QSPI1_IO[0:3]

Output

tOD

tOH

tOD

tLEAD

tLAG

tTD

tSU

MSB OUT

DATA

LSB OUT

IDLE

MSB IN

DATA

LSB IN

Figure 3.27

SDR Transfer Format Transmission and Reception Timing

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