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RZ/G2LC Datasheet(PDF) 15 Page - Renesas Technology Corp |
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RZ/G2LC Datasheet(HTML) 15 Page - Renesas Technology Corp |
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15 / 74 page ![]() RZ/G2L Group, RZ/G2LC Group 1. Overview R01DS0484EJ0110 Rev.1.10 Page 15 of 74 May 30, 2025 Shared L3$ 256 Kbytes Cortex-A55 MPCore CPG PLL/SSCG DDR3L/DDR4 SDRAM Sound Interface VCP ISU SDHI / eMMC External Memory Storage and Network MTU3a GPT WDT (3ch) I2C (4ch) SCIF (5ch) SCI/IrDA (1ch) RSPI (3ch) Analog Security PWM Timer Peripheral USB2.0 Host USB2.0 Host / Function GbEthernet GbEthernet CAN (2ch) SSIF (4ch) ADC (8ch) TrustedSecureIP (Option) OTP GPIO TSU (1 ch) Video Processing Mali-G31 ACPU Bus GIC SDHI System Secure DMAC (16 ch) On-Chip RAM 64 Kbytes Network System Timer SCI (1 ch) GTM (3 ch) Internal Memory MHU Multi CPU System System Graphics Processing (3DGE) DMAC (16 ch) LCD Controller Camera Interface Display Interface CRU VSPD DU MIPI CSI-2 Parallel Input MIPI DSI Parallel Output FCPVD SYC FCPCS VCPL4 Core 0 I$ 32 Kbytes NEON D$ 32 Kbytes Crypto (Option) Core 1 (Option) I$ 32 Kbytes NEON D$ 32 Kbytes Crypto (Option) Cortex-M33 MPU CoreSight Debug On-Chip RAM 64 Kbytes Internal Memory SPI Multi I/O External Memory Figure 1.1 Configuration of LSI Internal Bus |
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