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PSD4235G2 Datasheet(PDF) 75 Page - STMicroelectronics |
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PSD4235G2 Datasheet(HTML) 75 Page - STMicroelectronics |
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75 / 89 page  75/89 PSD4235G2 Table 64. Input Macrocell Timing Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX . Figure 43. Input Macrocell Timing (product term clock) Symbol Parameter Conditions -70 -90 PT Aloc Turbo Off Unit Min Max Min Max tIS Input Setup Time (Note 1) 00 ns tIH Input Hold Time (Note 1) 15 20 + 12 ns tINH NIB Input High Time (Note 1) 912 ns tINL NIB Input Low Time (Note 1) 912 ns tINO NIB Input to Combinatorial Delay (Note 1) 34 46 + 2 + 12 ns tINH tINL tINO tIH tIS PT CLOCK INPUT OUTPUT AI03101 |
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