PSD4235G2 datasheet(58/89 Pages) STMICROELECTRONICS

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PSD4235G2

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Figure 31. Port E, F and G Structure

Port F – Functionality and Structure

Port F can be configured to perform one or more

of the following functions:

MCU I/O Mode

CPLD Output – External Chip Select (ECS7-

ECS0) can be connected to Port F or Port C.

CPLD Input – direct input to the CPLD, no Input

Macrocells (IMC)

Latched Address output – Provide latched

address output as per Table 41.

Slew Rate – pins can be configured for fast Slew

Rate

Data Port – connected to D7-D0 when Port F is

configured as Data Port for a non-multiplexed

bus

Peripheral Mode

MCU Reset Mode – for 16-bit Motorola 683xx

and HC16 MCUs

Port G – Functionality and Structure

Port G can be configured to perform one or more

of the following functions:

MCU I/O Mode

Latched Address output – Provide latched

address output as per Table 41.

Open Drain – pins can be configured in Open

Drain Mode

Data Port – connected to D15-D8 when Port G

is configured as Data Port for a non-multiplexed

bus

MCU Reset Mode – for 16-bit Motorola 683xx

and HC16 MCUs

DATA OUT

ADDRESS

Ext. CS (Port F)

ENABLE PRODUCT TERM (.OE)

ALE

READ MUX

CPLD - INPUT (Port F)

CONTROL Register

DIR Register

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT Pin

DATA OUT

ADDRESS

A[ 7:0] OR A[15:8]

AI04938

ISP or Battery Back-Up (Port E)

Configuration Bit

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