DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
11
Version: DM9010-DS-P03
Apr. 28, 2005
5. Pin Description
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,
LI= reset Latch Input, #= asserted low, PD=internal pull-low about 60K ohm, PU=internal pull-high
5.1 MII Interface
Pin No.
Pin Name
I/O
Description
37
LINK_I
I,PD
External MII device link status
41,40,39,
38
RXD [3:0]
I,PD
External MII Receive Data
4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode
43
CRS
I/O,PD External MII Carrier Sense
Active high to indicate the pressure of carrier, due to receive or transmit activities
in 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface.
44
COL
I/O,PD External MII Collision Detect. This pin is output in reverse MII interface.
45
RX_DV
I,PD
External MII Receive Data Valid
46
RX_ER
I,PD
External MII Receive Error
47
RX_CLK
I,PD
External MII Receive Clock
49
TX_CLK
I/O,PD External MII Transmit Clock. This pin in output in MII interface.
53,52,51,
50
TXD [3:0]
O,PD External MII Transmit Data
4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps
nibble mode
TXD [2:0] is also used as the strap pins of IO base address.
IO base = (strap pin value of TXD [2:0]) * 10H + 300H
54
TX_ EN
O,PD External MII Transmit Enable
56
MDIO
I/O,PD MII Serial Management Data
57
MDC
O,PD MII Serial Management Data Clock
This pin is also used as the strap pin of the polarity of the INT pin
When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin
is high active
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