DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
34
Version: DM9010-DS-P03
Apr. 28, 2005
8.3 PHY ID Identifier Register #1 (PHYID1) - 02
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9010. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default
Description
2.15-2.0
OUI_MSB
<0181h>
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15
to 0 of this register respectively. The most significant two
bits of the OUI are ignored (the IEEE standard refers to these
as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) - 03
Bit
Bit Name
Default
Description
3.15-3.1
0
OUI_LSB
<101110>,
RO/P
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10
of this register respectively
3.9-3.4
VNDR_MDL
<001010>,
RO/P
Vendor Model Number
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
3.3-3.0
MDL_REV
<0000>,
RO/P
Model Revision Number
Five bits of vendor model revision number mapped to bit 3
to 0 (most significant bit to bit 4)
8.5 Auto-negotiation Advertisement Register (ANAR) - 04
This register contains the advertised abilities of this DM9010 device as they will be transmitted to its
link partner during Auto-negotiation.
Bit
Bit Name
Default
Description
4.15
NP
0,RO/P
Next page Indication
0 = No next page available
1 = Next page available
The DM9010 has no next page, so this bit is permanently set
to 0
4.14
ACK
0,RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9010's auto-negotiation state machine will
automatically control this bit in the outgoing FLP bursts and
set it at the appropriate time during the auto-negotiation
process. Software should not attempt to write to this bit.
4.13
RF
0, RW
Remote Fault
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