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AD4002 Datasheet(PDF) 6 Page - Analog Devices

Part # AD4002
Description  18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs
PDF  39 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4002 Datasheet(HTML) 6 Page - Analog Devices

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AD4002/AD4006/AD4010
Data Sheet
Rev. A | Page 6 of 39
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL OUTPUTS
Data Format
Serial 18 bits, straight binary
Pipeline Delay
Conversion results available
immediately after completed
conversion
Output Low Voltage, VOL
Output current = 500 μA
0.4
V
Output High Voltage, VOH
Output current = −500 μA
VIO − 0.3
V
POWER SUPPLIES
VDD
1.71
1.8
1.89
V
VIO
1.71
5.5
V
Standby Current
VDD and VIO = 1.8 V, TA = 25°C
1.6
μA
Power Dissipation
VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V
10 kSPS, high-Z mode disabled
70
μW
500 kSPS, high-Z mode disabled
3.5
4.4
mW
1 MSPS, high-Z mode disabled
7
8.4
mW
2 MSPS, high-Z mode disabled
14
16.5
mW
500 kSPS, high-Z mode enabled
3.8
5.4
mW
1 MSPS, high-Z mode enabled
7.6
10.8
mW
2 MSPS, high-Z mode enabled
15.2
21.5
mW
VDD Only
500 kSPS, high-Z mode disabled
2.5
mW
1 MSPS, high-Z mode disabled
4.9
mW
2 MSPS, high-Z mode disabled
9.75
mW
REF Only
500 kSPS, high-Z mode disabled
0.95
mW
1 MSPS, high-Z mode disabled
1.9
mW
2 MSPS, high-Z mode disabled
3.65
mW
VIO Only
500 kSPS, high-Z mode disabled
0.1
mW
1 MSPS, high-Z mode disabled
0.2
mW
2 MSPS, high-Z mode disabled
0.6
mW
Energy per Conversion
7
nJ/sample
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−40
+125
°C
1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the
AD4002, 1 MSPS for the AD4006, and 500 kSPS for the AD4010.
2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
3 Transient response is the time required for the ADC to acquire a full-scale input step to ±2 LSB accuracy. See Figure 43 for more information on ADC input settling for
multiplexed applications.
4 The minimum and maximum values are guaranteed by characterization, but not production tested.
5 See the 1/f noise plot in Figure 25.



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