AD4002 datasheet(23/39 Pages) AD

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Data Sheet

AD4002/AD4006/AD4010

Rev. A | Page 23 of 39

Multiplexed Applications

The AD4002/AD4006/AD4010 significantly reduce system

complexity for multiplexed applications that require superior

performance in terms of noise, power, and throughput. Figure 42

shows a simplified block diagram of a multiplexed data acquisition

system including a multiplexer, an ADC driver, and the precision

SAR ADC.

SAR ADC

ADC

DRIVER

MULTIPLEXER

Figure 42. Multiplexed Data Acquisition Signal Chain Using the

AD4002/AD4006/AD4010

Switching multiplexer channels typically results in large voltage

steps at the ADC inputs. To ensure an accurate conversion

result, the ADC step must be given adequate time to settle

before the ADC samples the inputs (on the subsequent rising

edge of CNV). The settling time error is dependent on the drive

circuitry (multiplexer and ADC driver), RC filter values, and

the time when the multiplexer channels are switched. Switch the

multiplexer channels immediately after tQUIET1 has elapsed from

the start of the conversion to maximize settling time and to

prevent corruption of the conversion result. To avoid conversion

corruption, do not switch the channels during the tQUIET1 time.

If the analog inputs are multiplexed during the quiet conversion

time (tQUIET1), the current conversion is possibly corrupted.

Figure 43 shows the conversion error vs. settling time when

switching between positive and negative full-scale inputs

(described in Table 9). The conversion error refers to the

deviation between the expected and actual code output for

either a positive or negative full-scale input.

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

ACQUISITION TIME (µs)

+FS TO ‒FS

‒FS TO +FS

Figure 43. Conversion Error vs. Settling Time with Full-Scale Input Steps,

VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, TA = 25°C

EASE OF DRIVE FEATURES

Input Span Compression

In single-supply applications, it is recommended to use the

full range of the ADC. However, the amplifier can have some

headroom and footroom requirements, which can be a problem,

even if it is a rail-to-rail input and output amplifier. The AD4002/

AD4006/AD4010 include a span compression feature, which

increases the headroom and footroom available to the amplifier

by reducing the input range by 10% from the top and bottom

of the range while still accessing all available ADC codes (see

Figure 44). The SNR decreases by approximately 1.9 dB (20 ×

log(8/10)) for the reduced input range when span compression

is enabled. Span compression is disabled by default but is enabled

by writing to the relevant register bit (see the Digital Interface

section).

ADC

VREF = 4.096V

DIGITAL OUTPUT

ALL 2N

CODES

+FSR

–FSR

90% OF VREF = 3.69V

10% OF VREF = 0.41V

ANALOG

INPUT

IN+

Figure 44. Span Compression

High-Z Mode

The AD4002/AD4006/AD4010 incorporate high-Z mode, which

reduces the nonlinear charge kickback when the capacitor DAC

switches back to the input at the start of acquisition. Figure 28

shows the input current of the AD4002/AD4006/AD4010 with

high-Z mode enabled and disabled. The low analog input current

makes the ADC easier to drive than the traditional SAR ADCs,

even with high-Z mode disabled. The input current reduces further

to submicroampere range when high-Z mode is enabled. High-Z

mode is disabled by default but can be enabled by writing to the

configuration register (see Table 12). Disable high-Z mode for

input frequencies above 100 kHz or when multiplexing.

To achieve the optimum data sheet performance from traditional

high resolution precision SAR ADCs, system designers must

often use a dedicated high power, high speed amplifier to drive

the switched capacitor SAR ADC inputs. High-Z mode allows a

choice of lower power and lower bandwidth precision amplifiers

with a lower RC filter cutoff to drive the ADC, removing the

need for dedicated high speed ADC drivers, which saves system

power, size, and cost in precision, low bandwidth applications.

High-Z mode allows the amplifier and RC filter in front of the

ADC to be chosen based on the signal bandwidth of interest,

rather than the settling requirements of the switched capacitor

SAR ADC inputs. High-Z mode also improves THD performance

and reduces analog input current for input signals up to 100 kHz.

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