TDA7333N datasheet(16/36 Pages) STMICROELECTRONICS

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Functional description

TDA7333N

16/36

3.6

Flywheel mechanism

Figure 6.

Example for flywheel mechanism

Within group and block synchronization control block a 6 bit (64 states) flywheel counter is

implemented to control RDS synchronization. After reset or a forced resynchronization by

setting “ar_res” bit rds_int[5], this counter increments from zero to one, if a valid RDS block

was detected. Valid means the syndrome has to be zero (“synz” = 1 rds_qu[0]) without any

error corrections done on good quality marked RDS bits. Then the RDS module is

synchronized. This is indicated by “synch” bit rds_int[4] which is set if the flywheel counter is

greater than zero. Every valid consecutive RDS block (A, B, C or C’, D, A, B...) increments

the flywheel counter by two.

If the next consecutive RDS block has its syndrome not zero, or corrections are done on

good quality marked RDS bits, then the flywheel counter decrements by one. If the flywheel

counter becomes zero, then a new RDS block synchronization will be performed. If blocks of

type E are detected (indicated by “e” bit rds_qu[1]), then the flywheel counter will be not

modified, because in case of European RDS, block E is an error but not in case of USA

BRDS. This means E blocks are treated as neutral in this RDS/BRDS implementation.

The “data_ok” bit rds_corrp[1] is set only, if the flywheel counter is greater than two, the

syndrome of the detected RDS block is zero and if no error corrections are done on good

quality marked RDS bits.

Figure 6 shows an example for the flywheel mechanism.

The first diagram shows the relative signal quality of 26 received RDS bits. 100 % means

that the last received 26 RDS bits are all marked as good by the demodulator and 0% that

all are marked as bad.

100

Signal

quality [%]

63(max)

Flywheel

counter

1.)

2.)

3.)

data_ok

synch

bne

interrupt

time

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