TDA7333N datasheet(24/36 Pages) STMICROELECTRONICS

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Functional description

TDA7333N

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3.8.6

rds_bd_ctrl register

3.8.7

sinc4reg register

3.8.8

testreg register

(7) Select sensitivity of quality bit.

00: minimum (reset value)

11: maximum

(8) Bit 5 "ar_res" of rds_int register will clear the bits 0-

6 of the rds_bd_ctrl register.

Write into buffer if synchronized (refer to page 10-12) (8)

1: Write into buffer only if synchronized (reset value).

0: Write into buffer any incoming RDS block.

Select PLL time constants by software or hardware (8)

1: Software. Time constants are selected by pllb[1:0] respectively

pllf.

0: Hardware (reset value). Time constants automatically increase

after reset or resynchronization.

Set the 57 kHz pll time constant (5) (8).

Bit 0 of 1187.5 Hz pll time constant (6) (8).

Bit 1 of 1187.5 Hz pll time constant (6) (8).

Bit 0 of quality sensitivity (7) (8).

Bit 1 of quality sensitivity (7) (8).

Select internal master clock frequency (fsys):

1: 8.664 MHz.

0: 8.55 MHz (reset value).

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r/w

shw

syncw

pllb1

freq

qsens0

qsens1

pllb0

pllf

reset value

rds_bd_ctrl

pllf

(5)

lock time needed for 90 deg deviation

2 ms

10 ms

pllb1

pllb0

(6)

lock time needed for 90 deg deviation

5 ms (reset status)

15 ms

35 ms

76 ms

sinc4reg register is for internal use only. For application this register

must be always Þlled with zeros.

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r/w

reset value

sinc4reg

testreg register is for internal use only. For application this register

must be always Þlled with zeros.

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r/w

reset value

testreg

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