VOLTAGE REFERENCE

2.5

µs/div

10k

Ω

1nF

±5V

+2.5V

REF

OUT

Test Circuit:

DEMAGNETIZATION

DRV401-EP

NOTE:

The internal resistance of the compensation coil may prevent high compensation

amplifier may not overload with this current. However, a fast rate of change of the

primary current would be transmitted through transformer action and safely trigger the

overload flag.

The precision 2.5 V reference circuit offers low drift (typically 10 ppm/K) and is used for internal biasing; it is also

signal around it. This output is buffered for low impedance and tolerates sink and source currents of ±5 mA.

Capacitive loads can be directly connected, but generate ringing on fast load transients. A small series resistor of

a few ohms improves the response, especially for a capacitive load in the range of 1

µF. Figure 6 shows the

transient load regulation with 1 nF direct load.

The reference source is part of the integrated circuit and referenced to GND2. Large current pulses driving the

compensation coil can generate a voltage drop in the GND connection that would add on to the reference

voltage. Therefore, a low impedance GND layout is critical to handle the currents and the high bandwidth of this

IC.

Figure 6. Pulse Response Test Circuit and Scope Shot of Reference

Iron cores are not immune to residual (remanence) magnetism. The residual remanence can produce a signal

offset error, especially after strong current overload, which goes along with high magnetic field density.

Therefore, the DRV401 includes a signal generator for a demagnetization cycle. The digital control pin, DEMAG,

starts this cycle on demand after this pin is held high for at least 25.6

µs. Shorter pulses are ignored. The cycle

lasts for approximately 110 ms. During this time, the Error flag is asserted low to indicate that the output is not

valid. When DEMAG is high during power-on, a demagnetization cycle immediately initiates (12

µs) after

section).

The probe circuit is in normal operation and oscillates during the demagnetization cycle. The outputs PWM and

PWM are active accordingly.

A demagnetization cycle can be aborted by pulling DEMAG low, filtered by 25

µs to ignore glitches (see

Figure 7). In a typical circuit, the DEMAG pin may be connected to the positive supply, which enables a degauss

cycle every time the unit is powered on.

The degauss cycle is based on an internal clock and counter logic. The maximum current is limited by the

resistance of the connected coil in series with the shunt resistor. The DEMAG logic input requires a +5 V

CMOS-compatible signal.

20

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