DRV401AMDWPREP datasheet(26/33 Pages) TI

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POWER DISSIPATION

THERMAL PAD

DRV401-EP

SBVS104 – JANUARY 2008............................................................................................................................................................................................... www.ti.com

Using the thermally-enhanced PowerPAD™ SO package dramatically reduces the thermal impedance from

junction to case. This package is constructed using a down-set lead frame upon which the die is mounted, as

shown in Figure 9a and Figure 9b. This arrangement results in the lead frame being exposed as a thermal pad

on the underside of the package. Figure 9 shows the SO-20 package as an example. Because this thermal pad

has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good

thermal path away from the thermal pad.

The two outputs ICOMP1 and ICOMP2 are linear outputs. Therefore, the power dissipation on each output is

proportional to the current multiplied by the internal voltage drop on the active transistor. For ICOMP1 and ICOMP2,

this internal voltage drop is the voltage drop to VDD2 or GND, according to the current-conducting side of the

output.

Output short-circuits are particularly critical for the driver because the full supply voltage can be seen across the

conducting transistor, and the current is not limited by anything other than the current density limitation of the

FET. Permanent damage to the device can occur.

The DRV401 does not include temperature protection or thermal shut-down.

Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but

board layout greatly influences overall heat dissipation. Table 1 shows the thermal resistance (TJA) for the two

packages with the exposed thermal pad soldered to a normal PCB, as described in Technical Brief SLMA002,

PowerPAD Thermally-Enhanced Package. Documents are available for download at www.ti.com.

Table 1.

JA/JP Estimations According to EIA/JED51-7

SO–20

(1)

(2) Still Air

JA with Forced Airflow (150lfm

(3))

(1)

JP = junction-to-pad thermal resistance,

(2)

JA = junction-to-ambient thermal resistance,

(3)

lfm = linear foot per minute.

NOTE:

All thermal models have an accuracy 9

≈20%.

Measuring the temperature as close as possible to the exposed thermal pad is recommended. The relatively low

thermal impedance,

JP, of less than 10°C/W (with some additional °C/W to the temperature test point on the

PCB) allows good estimation of the junction temperature in the application.

The thermal pad on the PCB should contain nine or more vias for the SO package, where the solder pad on the

PCB

can

larger

than

the

exposed

pad

(for

example,

6.6

18 mm) as recommended in the application literature noted previously.

Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load

conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress

for proper long-term operation with a junction temperature well below +125°C.

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