TAS5705PAPR datasheet(48/71 Pages) TI

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TAS5705

SLOS549 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com

Table 7. Serial Control Interface Register Summary (continued)

NO. OF

INITIALIZATION

SUBADDRESS

CONTENTS

BYTES

VALUE

0x35

ch2_bq[5]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x36

ch2_bq[6]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x37

ch6_bq[0]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x38

ch6_bq[1]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x39

Reserved(4)

0x3A

DRC1 ae

u[31:26], ae[25:0]

0x0080 0000

DRC1 (1 – ae)

u[31:26], (1 – ae)[25:0]

0x0000 0000

0x3B

DRC1 aa

u[31:26], aa[25:0]

0x0080 0000

DRC1 (1 – aa)

u[31:26], (1 – aa)[25:0]

0x0000 0000

0x3C

DRC1 ad

u[31:26], ad[25:0]

0x0080 0000

DRC1 (1 – ad)

u[31:26], (1 – ad)[25:0]

0x0000 0000

0x3D

DRC2 ae

u[31:26], ae[25:0]

0x0080 0000

DRC 2 (1 – ae)

u[31:26], (1 – ae)[25:0]

0x0000 0000

0x3E

DRC2 aa

u[31:26], aa[25:0]

0x0080 0000

DRC2 (1 – aa)

u[31:26], (1 – aa)[25:0]

0x0000 0000

0x3F

DRC2 ad

u[31:26], ad[25:0]

0x0080 0000

DRC2 (1 – ad)

u[31:26], (1 – ad)[25:0]

0x0000 0000

0x40

DRC1-T

T1[31:0]

0xFDA2 1490

0x41

DRC1-K

u[31:26], k1[25:0]

0x0384 2109

0x42

DRC1-O

u[31:26], O1[25:0]

0x0008 4210

0x43

DRC2-T

T2[31:0]

0xFDA2 1490

0x44

DRC2-K

u[31:26], k2[25:0]

0x0384 2109

0x45

DRC2-O

u[31:26], O2[25:0]

0x0008 4210

0x46

DRC control

u[31:2], ch6_enable, ch1_5_enable

0x0000 0000

0x47–0x49

Reserved(4)

0x0000 0000

0x50

Bank update command register

0x0000 0000

0x51–0xFF

Reserved(4)

0x0000 0000

(4)

Reserved registers should not be accessed.

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