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TAS5705PAPR Datasheet(PDF) 51 Page - Texas Instruments

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Part # TAS5705PAPR
Description  20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC
PDF  71 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5705PAPR Datasheet(HTML) 51 Page - Texas Instruments

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SERIAL DATA INTERFACE REGISTER (0x04)
SYSTEM CONTROL REGISTER 2 (0x05)
TAS5705
www.ti.com ...................................................................................................................................................................................................... SLOS549 – JUNE 2008
The TAS5705 supports the serial data modes shown in Table 12. The default is 24-bit, I2S mode.
Table 12. Serial Data Interface Control Register (0x04) Format
RECEIVE SERIAL DATA
WORD
D7–D5
D4
D3
D2
D1
D0
INTERFACE FORMAT
LENGTH
Right-justified
16
000
0
0
0
0
0
Right-justified
20
000
0
0
0
0
1
Right-justified
24
000
0
0
0
1
0
I2S
16
000
0
0
0
1
1
I2S
20
000
0
0
1
0
0
I2S (1)
24
000
0
0
1
0
1
Left-justified
16
000
0
0
1
1
0
Left-justified
20
000
0
0
1
1
1
Left-justified
24
000
0
1
0
0
0
Reserved
000
0
1
0
0
1
Right-justified
18
000
0
1
0
1
0
Reserved
000
0
1
0
1
1
Reserved
000
0
1
1
0
0
Reserved
000
0
1
1
0
1
Reserved
000
0
1
1
1
0
Reserved
000
0
1
1
1
1
Reserved
000
1
0
0
0
0
I2S (32 fS SCLK)
16
000
1
0
0
1
1
Left-justified (32 fS SCLK)
000
1
0
1
1
0
Reserved
000
1
1
0
0
1
Reserved
000
1
1
0
1
1
Reserved
000
1
1
1
0
1
(1)
Default values are in bold.
Bit D6 is a control bit and bit D5 is a configuration bit.
When bit D6 is set low, the system starts playing; otherwise, the outputs are shut down.
Bit D5 defines the configuration of the system, that is, it determines what configuration the system runs in when
bit D6 is set low. When this bit is asserted, all channels are switching. Otherwise, only a subset of the PWM
channels run. The channels to shut down are defined in the shutdown group register (0x19). Bit D5 should only
be changed when bit D6 is set, meaning that it is only possible to switch configurations by resetting the DAP and
then restarting it again in the new configuration.
Bit D3 defines which volume register is used to control the volume of the HP_PWMx outputs when in headphone
mode. When set to 0, the HP volume register (0x0C) controls the volume of the headphone outputs when in
headphone mode. When bit D3 is set to 1, the channel volume registers (0x08–0x0B, 0x0D) are used for all
modes (line out, headphone, speaker).
Bits D2–D1 define the output modes. The default is speaker mode with the headphone mode selectable via the
external HPSEL terminal. The device can also be forced into headphone mode by asserting bit D1 (all other
PWM channels are muted). Asserting bit D2 puts the device into a pseudo-line-out mode where the HP_PWMx
and all other PWM channels are active. Bit D3 must also be asserted in this mode, and the HP_PWMx volume is
controlled with the main speaker output volume controls via registers 0x08–0x0B and 0x0D.
Copyright © 2008, Texas Instruments Incorporated
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