21

3390C–MICRO–7/05

AT89S2051/S4051

Notes:

1. The internal Y-address counter is reset to 00H on the rising/falling edge of RST.

2. A positive pulse on XTAL1 loads the address data on Port P1 into the X-address (page) register and resets the Y-address.

3. A positive pulse on XTAL1 advances the Y-address counter.

4. A low pulse on P3.2 loads data from Port P1 for the current address. If another P3.2 low pulse does not arrive within 150 µs,

programming starts.

5. Internally timed for 4 ms.

6. Internally timed for 2 ms.

7. 00H must be loaded into the X-address before executing this command.

8. Will read User Signature if X-address is 00H, will read Atmel Signature if X-address is 01H.

10. Atmel Signature Bytes:

Table 21-2.

Parallel Programming Mode Command Summary

Mode

Test Control

Test Selects

Data I/O

P3.2

RST

(1)

INC

P3.3

P3.4

P3.5

P3.7

P1.7-0

Chip Erase

(5)

1.0 µs

12V

L

H

L

L

L

XX

Load X-Address

(2)

H

12V

0.1 µs

H

L

H

H

D

IN

Page Write

(3)(4)(6)

Code Memory

1.0 µs

12V

0.1 µs

L

H

H

H

D

IN

Page Read

(3)

Code Memory

H

12V

0.1 µs

L

L

H

H

Page Write

(3)(4)(6)(7)

Sig. Row

1.0 µs

12V

0.1 µs

LLLL

D

IN

Page Read

(3)(8)(10)

Sig. Row

H

12V

0.1 µs

L

L

L

H

D

OUT

Write Fuse/Lock Bit

(5)(9)

1.0 µs

12V

L

HHHH

Read Fuse/Lock Bit

(9)

H12V

L

H

H

L

L

D

OUT

Bit 7

Bit 6

Bit 5

Bit 4

Bit 1

Bit 0

XTAL Osc Bypass

User Row Programming

x2 Clock

Serial Programming

Lock Bit 2

Lock Bit 1

Enable = 0/Disable = 1

Enable = 0/Disable = 1

Enable = 0/Disable = 1

Enable = 0/Disable = 1

Locked = 0/Unlocked = 1

Locked = 0/Unlocked = 1

AT89S2051:

Address

00H = 1EH

01H = 23H

02H = FFH

AT89S4051:

Address

00H = 1EH

01H = 43H

02H = FFH