AT89S2051-24SC datasheet(5/45 Pages) ATMEL

5 / 45 page

3390C–MICRO–7/05

AT89S2051/S4051

X2 Mode Description

The clock for the entire circuit and peripherals is normally divided by 2 before being used by the

CPU core and peripherals. This allows any cyclic ratio (duty cycle) to be accepted on XTAL1

input. In X2 mode this divider is bypassed. Figure 6-1 shows the clock generation block diagram.

Figure 6-1.

Clock Generation Block Diagram

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in

Table 7-1.

Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-

mented on the chip. Read accesses to these addresses will in general return random data, and

write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future

products to invoke new features. In that case, the reset or inactive values of the new bits will

always be 0.

÷ 2

(XTAL1)/2

X2 Mode

OSC

State Machine: 6 Clock Cycles

CPU Control

XTAL

XTAL1

AT89S2051-24SC Datasheet(PDF) 5 Page - ATMEL Corporation