CC1111F16RSP datasheet(61/240 Pages) TAOS

61 / 240 page

CC1110Fx / CC1111Fx

SWRS033E

Page 61 of 239

Instruction

ADD

ADDC

SUBB

MUL

DIV

RRC

RLC

SETB C

CLR C

CPL C

ANL C,bit

ANL C,/bit

ORL C,bit

ORL C,/bit

MOV C,bit

CJNE

“0” = Clear to 0, “1” = Set to 1, “x” = Set to 1/Clear to 0, “-“ = Not affected

Table 38: Instructions that Affect Flag Settings

11.5 Interrupts

The CPU has 18 interrupt sources. Each

source has its own request flag located in a

set of Interrupt Flag SFRs. Each interrupt can

be individually enabled or disabled. The

definitions of the interrupt sources and the

interrupt vectors are given in Table 39.

2S and USART1 share interrupts. On the

CC1111Fx USB shares interrupt with Port 2

inputs. The interrupt aliases for I

2S and USB

are listed in Table 40. However, in the

following sections the original interrupt names,

masks, and flags listed in Table 39 are the

ones used.

The interrupts are grouped into a set of priority

level groups with selectable priority levels.

The interrupt enable registers are described in

section 11.5.1 and the interrupt priority

settings are described in section 11.5.3 on

page 69.

11.5.1 Interrupt Masking

Each interrupt can be individually enabled or

disabled by the interrupt enable bits in the

Interrupt Enable SFRs IEN0, IEN1, and IEN2.

The Interrupt Enable SFRs are described

below and summarized in Table 39.

Note that some peripherals have several

events that can generate the interrupt request

associated with that peripheral. This applies to

P0, P1, P2, DMA, Timer 1, Timer 2, Timer 3,

Timer 4, and Radio. These peripherals have

interrupt mask bits for each internal interrupt

source in the corresponding SFRs. Note that

2S has its own interrupt enable bits even if it

has only one event per interrupt. For the

pherihperals that have their own mask bits,

one or more of these bits must be set for the

associated CPU interrupt flag to be asserted.

In order to use any of the interrupts in the

CC1110Fx/CC1111Fx the following steps must be

taken:

1. Clear interrupt flags (see section 11.5.2)

2. Set individual interrupt enable bit in the

peripherals SFR, if any

3. Set

the

corresponding

individual,

interrupt enable bit in the IEN0, IEN1,

or IEN2 registers to 1

4. Enable global interrupt by setting the

IEN0.EA = 1

5. Begin the interrupt service routine at the

corresponding vector address of that

interrupt. See Table 39 for addresses

CC1111F16RSP Datasheet(PDF) 61 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

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