DS80C320-ENG datasheet(82/175 Pages) DALLAS

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High-Speed Microcontroller User’s Guide

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ROMSIZE REGISTER SETTINGS Table 6-2

RMS2

RMS1

RMS0

Max. On-chip ROM

0KB

1KB

2KB

4KB

8KB

16KB

32KB

64KB

After reset, a device with internal program memory will reset the ROMSIZE bits to their default setting.

This will be the maximum amount of on-chip memory for that device. The procedure to reconfigure the

amount of on-chip memory is as follows:

1. Jump to a location in program memory that will be unaffected by the change,

2. Disable interrupts by clearing the EA bit (IE.7),

3. Write AAh to the Timed Access Register (TA;C7h),

4. Write 55h to the Timed Access Register (TA;C7h),

5. Modify the ROM Size Select bits (RMS2-RMS0),

6. Delay 2 machine cycles (2 NOP instructions),

7. Enable interrupts by setting the EA bit (IE.7).

If the 0KB of internal program memory setting is selected, extra precautions must be taken. In this case,

it will be necessary to duplicate the interrupt vector table in external program memory. This is because

the interrupt vector table is located in the lower 1KB of memory, and the device will automatically

redirect any fetches from the interrupt vector table to external memory. Care must be exercised when

assembling or compiling the program so that all the modules are located at the correct starting address,

including the interrupt vector table.

PROGRAM MEMORY INTERCONNECT

The program memory interconnect scheme for the High-Speed Microcontroller family is shown in Figure

6-1. This example uses the DS80C320 and one 32K x 8 EPROM. The Program Store Enable (PSEN)

signal is used to provide an output enable to the EPROM. It can also be used to provide a chip enable,

but this produces less favorable timing. The address LSB and data are multiplexed on port 0, and the

address MSB is provided on port 2. An external latch, shown in the diagram as a 74F373, is used to latch

the lower byte of the address to the memory device. The Address Latch Enable (ALE) signal controls the

timing of the latch so that the operation is performed in the proper sequence. The signals and relative

timing for a program access are shown in Figure 6-2.

When implementing a high-speed memory interface, the F series (or faster) logic should be used. HC

logic will have worst case propagation delays that are too long. Specifications for all devices should be

checked. More information on memory interface timing can be found in Application Note 57, DS80C320

Memory Interface Timing, and Application Note 85, High Speed Microcontroller Interface Timing.

The first product in the family, the DS80C320, provides an extremely high-speed interface to external

ROM or EPROM. This assures that the user can use the slowest, and least expensive, memory device for

a given crystal speed. The DS80C320 provides very fast slew rates, but controls ringing and overshoot.

Fast slew rates allow the maximum possible time for memory access. In most cases, however, these

aspects will be transparent to the user. Refer to the electrical specifications for exact timing of each

product.

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