DS80C320-ENG datasheet(97/175 Pages) DALLAS

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High-Speed Microcontroller User’s Guide

97 of 175

SPEED REDUCTION

The High-Speed Microcontroller is a fully CMOS 8051 compatible microcontroller.

It can use

significantly less power than other 8051 versions because it is more efficient. As an average, software

will run 2.5 times faster on the High-Speed Microcontroller than on other 8051 derivatives. Thus the

same job can be accomplished by slowing down the crystal by a factor of 2.5. For example, an existing

8051 design that runs at 12 MHz can run at approximately 4.8 MHz on the High-Speed Microcontroller.

At this reduced speed, the High-Speed Microcontroller will have lower power consumption than an 8051,

yet perform the same job.

Using the 2.5X factor, Table 7-2 shows the approximate speed at which the High-Speed Microcontroller

can accomplish the same work as an 8051. The exact improvement will vary depending on the actual

instruction mix. Available crystal speeds must also be considered.

Refer to Section 16 for information

on instruction timing.

CRYSTAL VS MIPS COMPARISON Table 7-2

ORIGINAL 8051

CRYSTAL SPEED

MIPS

HIGH–SPEED MICROCONTROLLER

CRYSTAL SPEED

3.57 MHz

0.3

1.4 MHz

7.37 MHz

0.6

2.9 MHz

11.0592 MHz

0.9

4.4 MHz

14.318 MHz

1.2

5.7 MHz

16 MHz

1.3

6.4 MHz

20 MHz

1.6

8 MHz

24 MHz

2.0

9.6 MHz

33 MHz

2.7

13.2 MHz

40 MHz

3.3

16 MHz

POWER MANAGEMENT MODES

Power consumption in CMOS microcontrollers is a function of operating frequency.

The Power

Management Mode (PMM) feature, available with some members of the High-Speed Microcontroller

family, allows software to dynamically match operating frequency and current consumption with the need

for processing power. Instead of the default 4 clocks per machine cycle, power management mode 1

(PMM1) and power management mode 2 (PMM2) utilize 64 and 1024 clocks per cycle respectively to

conserve power.

A number of special features have been added to enhance the function of the power management modes.

The switchback feature allows the device to almost instantaneously return to divide by 4 mode upon

acknowledgment of an external interrupt or a falling edge on a serial port receiver pin. The advantages of

this become apparent when one calculates the increased interrupt service time of a device operating in

PMM. In addition, a device operating in PMM would normally be unable to sample an incoming serial

transmission to properly receive it. The switchback feature, explained below, allows a device to return to

divide by 4 operation in time to receive incoming serial port data and process interrupts with no loss in

performance.

The DS87C520 and DS87C530 incorporate a Status register (STATUS;C5h) to prevent the device from

accidentally reducing the clock rate during the servicing of an external interrupt or serial port activity.

This register can be interrogated to determine if a high priority, low priority, or power fail interrupt is in

progress, or if serial port activity is occurring. Based on this information the software can delay or reject

a planned change in the clock divider rate.

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