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DS80C320-ENG Datasheet(PDF) 39 Page - Dallas Semiconductor

Part # DS80C320-ENG
Description  High-Speed Microcontroller User Guide
PDF  175 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS80C320-ENG Datasheet(HTML) 39 Page - Dallas Semiconductor

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High-Speed Microcontroller User’s Guide
39 of 175
Serial Port Control (SCON1)
7
6
5
4
3
2
1
0
SFR C0h
SM0/FE_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SM0-2
Bits 7-5
Serial Port 1 Mode. These bits control the mode of serial port 1 as shown
below. In addition, the SM0 and SM2 bits have secondary functions as Shown
below.
SM0
SM1
SM2
MODE
FUNCTION
LENGTH
PERIOD
0
0
0
0
Synchronous
8 bits
12tCLK
0
0
1
0
Synchronous
8 bits
4tCLK
0
1
X
1
Asynchronous
10 bits
Timer 1 baud rate
equation
1
0
0
2
Asynchronous
11 bits
64tCLK (SMOD=0)
32tCLK (SMOD=1)
1
0
1
2
Asynchronous w/ Multiprocessor
communication
11 bits
64tCLK (SMOD=0)
32tCLK (SMOD=1)
1
1
0
3
Asynchronous
11 bits
Timer 1 baud rate
equation
1
1
1
3
Asynchronous w/ Multiprocessor
communication
11 bits
Timer 1 baud rate
equation
SM0/FE_1
Bit 7
Framing Error Flag. When SMOD0 (PCON.6)=0, this bit (SM0) is used to
select the mode for serial port 1. When SMOD0 (PCON.6)=1, this bit (FE) will
be set upon detection of an invalid stop bit. When used as FE, this bit must be
cleared in software. Once the SMOD0 bit is set, modifications to this bit will
not affect the serial port mode settings.
Although accessed from the same
register, internally the data for bits SM0 and FE are stored in different locations.
SM1_1
Bit 6
No alternate function.
SM2-2
Bit 5
Multiple CPU Communications. The function of this bit is dependent on the
serial port 1 mode.
Mode 0: Selects 12 tCLK or 4tCLK period for synchronous port 1 data transfers.
Mode 1: When this bit is set, reception is ignored (RI_1) is not set) if invalid
stop bit received.
Mode 2/3: when this bit is set, multiprocessor communications are enabled in
mode 2 and 3. This will prevent RI_1 from being set, and an interrupt being
asserted, if the 9
th bit received is not 1.



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