 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TDA7505 Datasheet(PDF) 18 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
TDA7505 Datasheet(HTML) 18 Page - STMicroelectronics |
|
|
18 / 38 page  Electrical specifications TDA7505 18/38 4.4 SAI interface timing - receiver Figure 3. SAI interface timing - receiver 4.5 SAI interface timing - transmitter Figure 4. SAI interface timing - transmitter Table 11. SAI interface timing - receiver Timing Description Min Typ Max Unit TDSP (1) 1. TDSP = DSP master clock cycle time = 1/Fdsp Internal DSP clock period (typical 1/75MHz) 13.33 ns tsckr Minimum clock cycle 6 TDSP ns tlrckrs LRCKR setup time TDSP ns tlrckrh LRCKR hold time TDSP ns tsdid SDI setup time TDSP ns tsdih SDI hold time TDSP ns tsckrh Minimum SCKR high time 0.35 tsckr ns tsckrl Minimum SCKR low time 0.35 tsckr ns tsckr t sckrl t sdis t lrckrs t sckrh t lrckrh t sdih Valid LRCKR SDI0-2 SCKR Valid (RCKP=0) tsckt tscktl t lrckts tsckth t lrckth t dt Valid LRCKT SDO0-2 SCKT Valid (TCKP=0) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
