TDA7580 datasheet(10/39 Pages) STMICROELECTRONICS

10 / 39 page

Block diagram and electrical specifications

TDA7580

10/39

GNDSD

IFADC modulator analogue ground

Clean ground, to be star

connected to voltage

regulator ground

GNDOSC

Oscillator ground

Clean ground, to be star

connected to voltage

regulator ground

9XTI

High impedance oscillator input (quartz

connection) or clock input when in

Antenna Diversity slave mode

Maximum voltage swing

is VDD=3.3V

XTO

Low impedance oscillator output (quartz

connection)

VDDOSC

Oscillator power supply

3.3V

VDDMTR

Tuner reference clock and AGC keying

DAC power supply

1.8V

CKREFP

Tuner reference clock positive output.

FM 100kHz

AMEU 18kHz

With internal pull-up, on

at reset [PP]

Output

CKREFN

Tuner reference clock negative output.

FM 100kHz

AMEU 18kHz

With internal pull-up, on

at reset [PP]

Output

AGCKEY

DAC output for Tuner AGC keying

1.5kohm ±30% output

impedance. 1Vpp ±1%

output dynamic range

GNDMTR

Ground of the tuner reference clock buffer

and the AGC keying DAC

PROTSEL_SS

DSP0 GPIO for control serial interface

(low: SPI or high: I2C) selection at device

Bootstrap.

In SPI protocol mode, after boot

procedure, SPI slave select, otherwise

DSP0 GPIO0

5V tolerant

With internal pull-up, on

at reset [PP]

Input

SDA_MOSI

Control serial interface and RDS IO:

- SPI mode: slave data in or master data

out for main SPI & RDS SPI data in

- I2C mode: data for main I2C or RDS I2C

5V tolerant

With internal pull-up, on

at reset [PP]

Input

MISO

SPI slave data out or master data in for

main SPI and RDS SPI data out

DSP0 GPIO1

5V tolerant. With

internal pull-up, on at

reset [PP]

Input

SCL_SCK

Bit clock for Control Serial Interface and

RDS

5V tolerant. With

internal pull-up, on at

reset [PP]

Input

Table 5.

Pin description (continued)

N°

Name

Type

Description

Notes

After

Reset

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