PM6681ATR datasheet(20/47 Pages) STMICROELECTRONICS

20 / 47 page

Device description

PM6681A

20/47

7.2

Constant on time architecture

Figure 31

shows the simplified block diagram of a constant on time controller. A minimum

off-time constrain (350 ns typ.) is introduced to allow inductor valley current sensing on

synchronous switch. A minimum on-time (130 ns) is also introduced to assure the start-up

switching sequence.

PM6681A has a one-shot generator for each power section that turns on the high side

MOSFET when the following conditions are satisfied simultaneously: the PWM comparator

is high, the synchronous rectifier current is below the current limit threshold, and the

minimum off-time has timed out.

Once the on-time has timed out, the high side switch is turned off, while the synchronous

switch is turned on according to the anti-cross conduction circuitry management.

When the negative input voltage at the PWM comparator (Figure 31), which is a scaled-

down replica of the output voltage (see the external R1/R2 divider in Figure 32), reaches the

valley limit (determined by internal reference Vr = 0.9 V), the low-side MOSFET is turned off

according to the anti-cross conduction logic once again, and a new cycle begins.

Figure 31.

Constant on-time block diagram

7.3

Output ripple compensation and loop stability

In a classic constant on time control, the system regulates the valley value of the output

voltage and not the average value, as shown in Figure 30. In this condition, the output

voltage ripple is source of a DC static error.

To compensate this error, an integrator network can be introduced in the control loop, by

connecting the output voltage to the COMP1/COMP2 (for the OUT1 and OUT2 sections

respectively) pin through a capacitor CINT as in Figure 32.

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