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LFXP Datasheet(PDF) 49 Page - Lattice Semiconductor |
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LFXP Datasheet(HTML) 49 Page - Lattice Semiconductor |
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49 / 130 page  3-18 DC and Switching Characteristics Lattice Semiconductor LatticeXP Family Data Sheet LatticeXP Internal Timing Parameters 1 Over Recommended Operating Conditions Parameter Description -5 -4 -3 Units Min. Max. Min. Max. Min. Max. PFU/PFF Logic Mode Timing tLUT4_PFU LUT4 Delay (A to D Inputs to F Output) — 0.28 — 0.34 — 0.40 ns tLUT6_PFU LUT6 Delay (A to D Inputs to OFX Output) — 0.44 — 0.53 — 0.63 ns tLSR_PFU Set/Reset to Output of PFU — 0.90 — 1.08 — 1.29 ns tSUM_PFU Clock to Mux (M0,M1) Input Setup Time 0.13 — 0.15 — 0.19 — ns tHM_PFU Clock to Mux (M0,M1) Input Hold Time -0.04 — -0.03 — -0.03 — ns tSUD_PFU Clock to D Input Setup Time 0.13 — 0.16 — 0.19 — ns tHD_PFU Clock to D Input Hold Time -0.03 — -0.02 — -0.02 — ns tCK2Q_PFU Clock to Q Delay, D-type Register Configuration — 0.40 — 0.48 — 0.58 ns tLE2Q_PFU Clock to Q Delay Latch Configuration — 0.53 — 0.64 — 0.76 ns tLD2Q_PFU D to Q Throughput Delay when Latch is Enabled — 0.55 — 0.66 — 0.79 ns PFU Dual Port Memory Mode Timing tCORAM_PFU Clock to Output — 0.40 — 0.48 — 0.58 ns tSUDATA_PFU Data Setup Time -0.18 — -0.14 — -0.11 — ns tHDATA_PFU Data Hold Time 0.28 — 0.34 — 0.40 — ns tSUADDR_PFU Address Setup Time -0.46 — -0.37 — -0.30 — ns tHADDR_PFU Address Hold Time 0.71 — 0.85 — 1.02 — ns tSUWREN_PFU Write/Read Enable Setup Time -0.22 — -0.17 — -0.14 — ns tHWREN_PFU Write/Read Enable Hold Time 0.33 — 0.40 — 0.48 — ns PIC Timing PIO Input/Output Buffer Timing tIN_PIO Input Buffer Delay — 0.62 — 0.72 — 0.85 ns tOUT_PIO Output Buffer Delay — 2.12 — 2.54 — 3.05 ns IOLOGIC Input/Output Timing tSUI_PIO Input Register Setup Time (Data Before Clock) 1.35 — 1.83 — 2.37 — ns tHI_PIO Input Register Hold Time (Data After Clock) 0.05 — 0.05 — 0.05 — ns tCOO_PIO Output Register Clock to Output Delay — 0.36 — 0.44 — 0.52 ns tSUCE_PIO Input Register Clock Enable Setup Time -0.09 — -0.07 — -0.06 — ns tHCE_PIO Input Register Clock Enable Hold Time 0.13 — 0.16 — 0.19 — ns tSULSR_PIO Set/Reset Setup Time 0.19 — 0.23 — 0.28 — ns tHLSR_PIO Set/Reset Hold Time -0.14 — -0.11 — -0.09 — ns EBR Timing tCO_EBR Clock to Output from Address or Data — 4.01 — 4.81 — 5.78 ns tCOO_EBR Clock to Output from EBR Output Register — 0.81 — 0.97 — 1.17 ns tSUDATA_EBR Setup Data to EBR Memory -0.26 — -0.21 — -0.17 — ns tHDATA_EBR Hold Data to EBR Memory 0.41 — 0.49 — 0.59 — ns tSUADDR_EBR Setup Address to EBR Memory -0.26 — -0.21 — -0.17 — ns tHADDR_EBR Hold Address to EBR Memory 0.41 — 0.49 — 0.59 — ns tSUWREN_EBR Setup Write/Read Enable to EBR Memory -0.17 — -0.13 — -0.11 — ns tHWREN_EBR Hold Write/Read Enable to EBR Memory 0.26 — 0.31 — 0.37 — ns tSUCE_EBR Clock Enable Setup Time to EBR Output Register 0.19 — 0.23 — 0.28 — ns tHCE_EBR Clock Enable Hold Time to EBR Output Register -0.13 — -0.10 — -0.08 — ns |
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