LFXP datasheet(13/130 Pages) LATTICE

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2-10

Architecture

Lattice Semiconductor

LatticeXP Family Data Sheet

Figure 2-10. PLL Diagram

Figure 2-11 shows the available macros for the PLL. Table 2-11 provides signal description of the PLL Block.

Figure 2-11. PLL Primitive

Table 2-5. PLL Signal Descriptions

Signal

I/O

Description

CLKI

Clock input from external pin or routing

CLKFB

PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock

(PIN or logic)

RST

“1” to reset input clock divider

CLKOS

PLL output clock to clock tree (phase shifted/duty cycle changed)

CLKOP

PLL output clock to clock tree (No phase shift)

CLKOK

PLL output to clock tree through secondary clock divider

LOCK

“1” indicates PLL LOCK to CLKI

DDAMODE

Dynamic Delay Enable. “1” Pin control (dynamic), “0”: Fuse Control (static)

DDAIZR

Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on

DDAILAG

Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead

DDAIDEL[2:0]

Dynamic Delay Input

DDAOZR

Dynamic Delay Zero Output

DDAOLAG

Dynamic Delay Lag/Lead Output

DDAODEL[2:0]

Dynamic Delay Output

VCO

CLKOS

CLKOK

LOCK

RST

CLKFB

from CLKOP

(PLL internal),

from clock net

(CLKOP) or

from a user

clock (PIN or logic)

Dynamic Delay Adjustment

Input Clock

Divider

(CLKI)

Feedback

Divider

(CLKFB)

Post Scalar

Divider

(CLKOP)

Phase/Duty

Select

Secondary

Clock

Divider

(CLKOK)

Delay

Adjust

Voltage

Controlled

Oscillator

CLKI

(from routing or

external pin)

CLKOP

EPLLB

CLKOP

CLKI

CLKFB

LOCK

EHXPLLB

CLKOS

CLKI

CLKFB

CLKOK

LOCK

RST

CLKOP

DDAIZR

DDAILAG

DDA MODE

DDAIDEL[2:0]

DDAOZR

DDAOLAG

DDAODEL[2:0]

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