OR4E02 datasheet(86/152 Pages) LATTICE

86 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Timing Characteristics (continued)

Table 47. Primary CLK (PCLK) to Output Delay without on-chip PLLs (Pin-to-Pin)

OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +85 °C; CL = 30 p.

OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +100 °C; CL = 30 p.

Notes:

1. Timing is without the use of the phase-locked loops (PLLs).

2. This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the LVTTL (3.3 V) input clock buffer delay,

the clock routing to the PIO CLK input, the clock→Q of the FF, and the delay through the LVTTL (3.3 V) data output buffer. The PCLK input

clock is connected at the semi-dedicated primary clock input pins.

3. For timing improvements using other I/O buffer types for the input clock buffer or output data buffer, see Table 53 and Table 55.

5-4846(F).b

Figure 48. Primary Clock to Output Delay

Table 48. Primary CLK (PCLK) to Output Delay using on-chip PLLs (Pin-to-Pin)

OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +85 °C;

CL = 30 p.

OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +100 °C;

CL = 30 p.

Notes:

1. Timing uses the automatic delay compensation mode of the PLLs. The feedback to the PLL is provided by the global system clock routing.

Other delay values are possible by using the phase modifications mode of the PLL instead.

2. This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the LVTTL (3.3 V) input clock buffer delay,

a PLL block, the clock routing to the PIO CLK input, the clock→Q of the FF, and the delay through the LVTTL (3.3 V) data output buffer. The

PCLK input clock is connected at the semi-dedicated PLL input pin.

3. For timing improvements using other I/O buffer types for the input clock buffer or output data buffer, see Table 53 and Table 55.

Description

Device

Speed

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

PCLK Input Pin →OUTPUT Pin (LVTTL-12 mA Fast)

OR4E02

OR4E04

OR4E06

—

9.00

9.24

9.42

—

8.03

8.23

8.41

—

7.28

7.46

7.62

Description

Device

Speed

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

PCLK Input Pin →OUTPUT Pin (LVTTL-12 mA Fast)

OR4E02

OR4E04

OR4E06

—

5.53

5.54

5.53

—

5.00

—

4.54

4.55

4.54

PLL Delay Adjustments from Cycle Stealing (used to

reduce clk->out by the min delay value shown):

One Delay Cell

Two Delay Cells

Three Delay Cells

All

—

0.89

1.64

2.43

—

0.70

1.29

1.98

—

0.64

1.18

1.80

OUTPUT (30 pF LOAD)

PCLK

PIO FF

OR4E02 Datasheet(PDF) 86 Page - Lattice Semiconductor

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