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ORSPI4 Datasheet(PDF) 106 Page - Lattice Semiconductor |
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ORSPI4 Datasheet(HTML) 106 Page - Lattice Semiconductor |
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106 / 263 page ![]() Lattice Semiconductor ORCA ORSPI4 Data Sheet 106 SERDES Detailed Description The SERDES provides transceiver functionality for four serial data channels. Each channel is identified by a chan- nel identifier [A:D]. The data channels can operate independently or they can be combined together (aligned) to achieve higher bit rates. The mode operation of the core is defined by a set of control registers, which can be written through the sys- tem bus interface. Also, the status of the core is stored in a set of status registers, which can be read through the system bus interface. The transmitter section for each channel accepts 40 bits (RAW MODE) of data or 32-bits of data and eight con- trol/status bits from the FPGA logic and (optionally) encodes the data using 8b/10b encoding. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to synthesize the internal high-speed serial bit clock. The data is then serialized and the serialized data are available at the differential CML output terminated in 86 Ω to drive either an optical transmitter or coaxial media or circuit board/backplane. The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the clock recovery section, which generates a recovered clock and retimes the data. The retimed data are also de-seri- alized and optionally 8b/10b decoded. The receiver also (optionally) recognizes the comma characters or code vio- lations and aligns the bit stream to the proper word boundary. The resulting parallel data is (optionally) passed to the multi-channel alignment block before it is presented to the FPGA logic. 8b/10b Encoding and Decoding In 8b/10b mode, the FPGA logic will receive/transmit 32-bits of data and four K_CTRL bits from/to the embedded core. In the transmit direction, four additional input bits can force a negative disparity present state. The SERDES logic will encode the data to, or decode the data from, a 10-bit format according to the FC-PH ANSI X3.230:1994 standard (which is also the encoding used by the IEEE 802.3ae Ethernet standard). This encoding/decoding scheme also allows for the transmission of special characters and supports error detection. Following the definitions and conventions used in defining the 8b/10b coding rules, each valid coded character has a name corresponding to its 8-bit binary value: • Dx.y for data characters • Kx.y for special characters • x = the 5-bit input value, base 10, for bits ABCDE • y = the 3-bit input value, base 10, for bits FGH An 8b/10b encoder is designed to maintain a neutral average disparity. Disparity is the difference between the number of “1”s and “0”s in the encoded word. Neutral disparity indicates the number of “1”s and “0”s are equal. Positive disparity indicates more “1”s than “0”s. Negative disparity indicates more “0”s than “1”s. The average dis- parity determines the DC component of the signals on the serial line. Running disparity is a record of the cumula- tive disparity of every encoded word, and is tracked by the encoder. In order to maintain neutral disparity, two different codings are defined for each data value. The 8b/10b encoder in the transmit path selects between (+) and (-) encoded word based on calculated disparity of the present data to maintain neutral disparity. In the receive path, the clock and data recovery blocks retime the incoming data and 8b/10b decoders generate 8- bit data based on the received 10-bit data. A sequence of valid 8b/10b coded characters has a maximum run length of 5-bits (i.e., five consecutive “1”s or five consecutive “0”s before a mandatory bit transition). This assures adequate transitions for robust clock recovery. The recovered data is aligned on a 10-bit boundary by detecting and aligning to special characters in the incoming data stream. Data is word-aligned using the comma (/K/) character. A comma character is a special character that contains a unique pattern (0011111 or its complement 1100000) in the 10-bit space that makes it useful for delim- |
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