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ORSPI4 Datasheet(PDF) 182 Page - Lattice Semiconductor

Part # ORSPI4
Description  Dual SPI4 Interface and High-Speed SERDES FPSC
PDF  263 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ORSPI4 Datasheet(HTML) 182 Page - Lattice Semiconductor

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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
182
The dynamic alignment timing budget for a data transfer between two ORSPI4 devices is shown in Table 62.
Table 62. Data Path Parameters for Dynamic Alignment.
With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, 900 Mbit/s data rate with 112.5 Mhz REFCLK, REFCLK jitter of 30 ps,
TJ = -40º C to 125º C, 1.425 V to 1.575 V supply. Jitter measured with a Wavecrest SIA-3000.
SPI4.2 Status Interface
System Timing Reference Points
Figure 93 shows the system timing reference points A and B for status channel timing parameters listed in Table
63.
Figure 93. Status Channel Reference Points
Figure 94. Status Channel Reference Points with Respect to Clock Edge (LVDS and LVTTL I/Os)
Description
Value
(UI peak-to-peak)
Transmit clock jitter
0.11
Transmit data jitter with respect to clock edge
0.09
Receive clock jitter tolerance
0.60
Source
Sink
TSTAT[1:0] /
RSTAT[1:0]
TSCLK/RSCLK
DC
Note: Only status signals are shown
RSCLK
RSTAT
(C)
Launch Edge
T
dia
T
dib
(D)
Capture Edge
t
s
t
h
TSCLK
TSTAT



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