M306N5FCFP datasheet(73/88 Pages) RENESAS

73 / 88 page

Rev.2.40

Aug 25, 2006

page 73 of 84

REJ03B0004-0240

M16C/6N Group (M16C/6N5)

5. Electric Characteristics (Normal-ver.)

Under development

This document is under development and its contents are subject to change.

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK)

(3)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR)

(3)

__________

HLDA output delay time

Symbol

Parameter

Min.

Standard

Unit

Max.

(NOTE 1)

–4

(NOTE 2)

(NOTE 1)

Switching Characteristics

(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 5.66 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5

✕ 109

f(BCLK)

– 10 [ns]

2. Calculated according to the BCLK frequency as follows:

0.5

✕ 109

f(BCLK)

– 40 [ns]

3. This standard value shows the timing when the

output is off, and does not show hold time of

data bus.

Hold time of data bus varies with capacitor volume

and pull-up (pull-down) resistance value.

Hold time of data bus is expressed in

t = – CR

✕ ln (1 – VOL / VCC)

by a circuit of the right figure.

For example, when VOL = 0.2 VCC, C = 30 pF,

R =1 k

Ω, hold time of output “L” level is

t = – 30 pF

✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.

Figure 5.21 Port P0 to P10 Measurement Circuit

DBi

30 pF

P10

Measuring

Condition

Figure 5.21

f(BCLK) is 12.5 MHz or less.

VCC = 3.3 V

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