7542 datasheet(59/122 Pages) RENESAS

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7542 Group

Rev.3.03

Jul 11, 2008

Page 59 of 117

REJ03B0006-0303

Reset Circuit

The 7542 group starts operation by the on-chip oscillator after sys-

tem is released from reset.

Accordingly, when the rising of power supply voltage passes 2.2V,

set the reset input voltage to become below 0.2Vcc (0.44V).

Moreover, switch CPU clock to the external oscillator after the ris-

ing of power supply voltage passes the minimum operation

voltage and after an oscillation is stabilized.

Note: The minimum operation voltage is decided by the division

ratio of an external oscillator's frequency and a CPU clock.

Decide on an external oscillator's oscillation stabilizing time

after fully evaluating an oscillator's stabilizing time used.

Fig. 73 Example of reset circuit

Fig. 74 Timing diagram at reset

(Note)

0.2 VCC

0 V

Poweron

VCC

RESET

VCC

RESET

Power source

voltage

detection circuit

Power source

voltage

Reset input

voltage

Note : Reset release voltage Vcc = 2.2 V

Data

Address

8-13 clock cycles

Reset address from the

vector table

1 : An on-chip oscillator applies about RING•2 MHz, φ•250 kHz frequency clock

at average of Vcc = 5 V.

2 : The mark “?” means that the address is changeable depending on the previous state.

3 : These are all internal signals except RESET.

Notes

FFFC

FFFD

ADH,ADL

ADL

ADH

Clock from

on-chip oscillator

RING

RESET

RESETOUT

SYNC

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