7560 datasheet(29/71 Pages) RENESAS

29 / 71 page

Rev.1.02

Jul 31, 2003

page 29 of 69

7560 Group (A version)

Timer 1, Timer 2, Timer 3

Timer 1, timer 2, and timer 3 are 8-bit timers and is equipped with

the timer latch. The count source for each timer can be selected

by the timer 123 mode register.

The division ratio of each timer is given by 1/(n+1), where n is the

value in the timer latch. All timers are down-counters. When the

contents of the timer reach “0016”, an underflow occurs at the next

count pulse and the contents of the timer latch are reloaded into

the timer and the count is continued. When the timer underflows,

the interrupt request bit corresponding to that timer is set to “1”.

When a value is written to the timer 1 register and the timer 3 reg-

ister, a value is simultaneously set as the timer latch and the timer.

When the timer 1 register, the timer 2 register, or the timer 3 regis-

ter is read, the count value of the timer can be read.

●Timer 2 Write Control

Which write can be selected by the timer 2 write control bit (bit 2)

of the timer 123 mode register (address 002916), writing data to

both the latch and the timer at the same time or writing data only

to the latch. When the operation “writing data only to the latch” is

selected, the value is set to the timer 2 latch by writing data to the

timer 2 register and the timer 2 is updated at next underflow. After

reset, the operation “writing data to both the latch and the timer at

the same time” is selected, and the value is set to both the timer 2

latch and the timer 2 at the same time by writing data to the timer

2 register.

If the value is written in latch only, a value is simultaneously set to

the timer 2 and the timer 2 latch when the writing in the high-

order register and the underflow of timer 2 are performed at the

same timing.

●Timer 2 Output Control

When the timer 2 (TOUT) output is enabled by the TOUT/

φ output

enable bit and the TOUT/φ output selection bit, an inversion signal

from the TOUT pin is output each time timer 2 underflows.

In this case, set the P43/φ/TOUT pin to output mode (set “1” to bit 3

of port P4 direction register).

■Note on Timer 1 to Timer 3

When the count source of timers 1 to 3 is changed, the timer

counting value may become arbitrary value because a thin pulse

is generated in count input of timer. If timer 1 output is selected as

the count source of timer 2 or timer 3, when timer 1 is written, the

counting value of timer 2 or timer 3 may become undefined value

because a thin pulse is generated in timer 1 output.

Therefore, set the value of timer in the order of timer 1, timer 2

and timer 3 after the count source selection of timer 1 to 3.

Fig. 25 Structure of timer 123 mode register

TOUT output active edge switch bit

0 : Start at “H” output

1 : Start at “L” output

TOUT/φ output enablel bit

0 : TOUT/φ output disabled

1 : TOUT/φ output enabled

Timer 2 write control bit

0 : Write data in latch and counter

1 : Write data in latch only

Timer 2 count source selection bit

0 : Timer 1 output signal

1 : f(XIN)/16

(or f(XCIN)/16 in low-speed mode)

Timer 3 count source selection bit

0 : Timer 1 output signal

1 : f(XIN)/16

(or f(XCIN)/16 in low-speed mode)

Timer 1 count source selection bit

0 : f(XIN)/16

(or f(XCIN)/16 in low-speed mode)

1 : f(XCIN)

Not used (“0” at reading)

Timer 123 mode register

(T123M :address 002916)

Note: System clock φ is f(XCIN)/2 in the low-speed mode.

7560 Datasheet(PDF) 29 Page - Renesas Technology Corp

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