M37545RLSS datasheet(45/62 Pages) RENESAS

45 / 62 page

Rev.1.06

Mar 07, 2008

Page 45 of 59

REJ03B0140-0106

7545 Group

NOTES ON USE

Countermeasures Against Noise

1. Shortest wiring length

(1) Package

Select the smallest possible package to make the total wiring

length short.

The wiring length depends on a microcomputer package. Use of

a small package, for example QFP and not DIP, makes the total

wiring length short to reduce influence of noise.

Fig. 48 Selection of packages

(2) Wiring for RESET pin

Make the length of wiring which is connected to the RESET pin

as short as possible. Especially, connect a capacitor across the

RESET pin and the VSS pin with the shortest possible wiring

(within 20mm).

The width of a pulse input into the RESET pin is determined by

the timing necessary conditions. If noise having a shorter pulse

width than the standard is input to the RESET pin, the reset is

released before the internal state of the microcomputer is

completely initialized. This may cause a program runaway.

Fig. 49 Wiring for the RESET pin

(3) Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O pins

as short as possible.

• Make the length of wiring (within 20 mm) across the

grounding lead of a capacitor which is connected to an

oscillator and the VSS pin of a microcomputer as short as

possible.

• Separate the VSS pattern only for oscillation from other VSS

patterns.

If noise enters clock I/O pins, clock waveforms may be

deformed. This may cause a program failure or program

runaway. Also, if a potential difference is caused by the noise

between the VSS level of a microcomputer and the VSS level of

an oscillator, the correct clock will not be input in the

microcomputer.

Fig. 50 Wiring for clock I/O pins

(4) Wiring to CNVSS pin

Connect CNVSS pin to a GND pattern at the shortest distance.

The GND pattern is required to be as close as possible to the

GND supplied to VSS.

In order to improve the noise reduction, to connect a 5 k

Ω

resistor serially to the CNVSS pin - GND line may be valid.

As well as the above-mentioned, in this case, connect to a GND

pattern at the shortest distance. The GND pattern is required to

be as close as possible to the GND supplied to VSS.

The CNVSS pin of the QzROM is the power source input pin for

the built-in QzROM. When programming in the built-in

QzROM, the impedance of the CNVSS pin is low to allow the

electric current for writing flow into the QzROM. Because of

this, noise can enter easily. If noise enters the CNVSS pin,

abnormal instruction codes or data are read from the built-in

QzROM, which may cause a program runaway.

Fig. 51 Wiring for the VPP pin of the QzPROM

DIP

SDIP

SOP

QFP

RESET

Reset

circuit

Noise

VSS

Reset

circuit

VSS

RESET

VSS

N.G.

O.K.

Noise

XIN

XOUT

VSS

XIN

XOUT

VSS

N.G.

O.K.

About 5k

Ω

VSS

The shortest

CNVSS/VPP

(Note)

Note: This indicates pin.

M37545RLSS Datasheet(PDF) 45 Page - Renesas Technology Corp

M37545RLSS Datasheet(HTML) 45 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL