HSYNC

(in)

VSYNC

(in)

CKREF

YCRCB

Cb

Y

Cr

Y’

Cb

Active Edge (programmable polarity)

Active Edge (programmable polarity)

Notes : 1. This figure is valid for bits “syncin_ad[1:0]” = default.

2. The active edges of HSYNC and VSYNC should normally be simultaneous. It is permissible that HSYNC transitions before

VSYNC, but VSYNC must not transition before HSYNC.

Figure 12 : HSYNC + VSYNC Based Slave Mode Sync Signals

ODDEVEN

(in)

CKREF

YCRCB

Cb

Y

Cr

Y’

Cb

Active Edge (programmable polarity)

Note :

1. This figure is valid for bits “syncin_ad[1:0]” = default.

Figure 13 : ODDEVEN Based Slave Mode Sync Signals

IV - FUNCTIONAL DESCRIPTION (continued)

IV.5.2- Synchronization onto a Frame Sync Signal

IV.5.2.1 - ODDEV-only Based Synchronization

Synchronization is performed on a frame-by-frame

basis by locking onto an incoming ODDEV signal.

A line sync signal is derived internally and is also

output as HSYNC. Refer to Figure 13 for wave-

forms and timings. The phase relationship between

ODDEV and the incoming YCrCB data is normally

such that the first clock rising edge following the

ODDEV active edge samples “Cb” (i.e. a ‘blue’

chroma sample within the YCrCb stream). It is

however possible to internally delay the incoming

ODDEV signal by up to 3 clock cycles to cope with

different data/sync phasings, using configuration

bits “Syncin_ad” (Reg. 4).

The first active edge of ODDEV triggers generation

of the analog sync signals and encoding of the

incomingvideo data. Frames being supposed to be

of constant duration, the next ODDEV active tran-

sition is expected at a precise time after the last

ODDEV detected.

So, once an active ODDEV edge has been de-

tected, checks that the following ODDEV are pre-

sent at the expected instants are performed.

Encoding and analog sync generation carry on un-

less three successive fails of these checks occur.

In that case, three behaviors are possible, accord-

ing to the configuration programmed (Reg. 1-2) :

- if ‘free-run’ is enabled, the STV0118 carries on

outputting the digital line sync HSYNC and gene-

rating analog video just as though the expected

ODDEV edge had been present. However, it will

re-synchronize onto the next ODDEV active edge

detected, whatever its location.

- if ‘free-run’ is disabled but bit ‘sync_ok’ is set in

configuration register1, the STV0118 sets the

active portion of the TV line to black level but

carries on outputting the analog sync tips (on Ys

and CVBS) and the digital line sync signal

HSYNC.

- if ‘free-run’ is disabled and the bit ‘sync_ok’ is not

set, all analog video is at black level and neither

analog sync tips nor digital line sync are output.

Note that this mode is a frame-based sync mode,

as opposedto a field-basedsync mode, that is, only

one type of edge (rising or falling, according to bit

‘polv’in Reg 0) is of interest to the STV0118, the

other one is ignored.

STV0118

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