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STV2001 Datasheet(PDF) 25 Page - STMicroelectronics |
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STV2001 Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 46 page ![]() STV2001 25/46 14.1.8 - Sync Processor Output The sync processor indicates whether 1st PLL is locked to an incoming horizontal sync or not. This is indicated on the D8 bit of the status register . PLL1 level is low when locked. 14.2 - HORIZONTAL PART 14.2.1 - Internal Input Conditions A digital signal (horizontal sync pulse) is sent by the sync processor to the horizontal input. It must be positive (see Figure 5). Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7 µs. Vertical synchro extraction is not allowed. Figure 5. 14.2.2 - PLL1 The PLL1 consists of a phase comparator, an ex- ternal filter and a voltage-controlled oscillator (VCO). The phase comparator is a "phase fre- quency" type designed in CMOS technology. This kind of phase detector avoids locking on wrong frequencies. It is followed by a "charge pump", composed of two current sources: sunk and sourced (typically I =1 mA when locked and I= 40 µA when unlocked). This difference be- tween lock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is rein- forced by an internal original slow down system when PLL1 is locked, preventing the horizontal fre- quency from changing too quickly. The dynamic behaviour of PLL1 is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 6). One bit I2C Ipump is used to set the pump current to 1mA or 0.3mA in locked condition. Figure 6. Figure 7. Block Diagram ²& Z T PLL1F 40 1.8k Ω 10nF 4.7 µF Lock/Unlock Status PHASE ADJUST Low High LOCKDET COMP1 CHARGE PUMP PLL1F R0 C0 40 41 42 VCO OSC I2C HPOS Adj. 1 44 FILTER 43 FC1 I2C Ipump |
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