M65665CFP/SP

Rev.2.00, Sep.04.2003, page 13 of 17

The relation of input signal 32-pin (Main-HD) and 33-pin (Main-VD) is shown below

32-pin input

(Main-HD)

33-pin input

(Main-VD)

[Even to Odd]

+10

µsec

-10

µsec

+21.75

µsec

+41.75

µsec

33-pin input

(Main-VD)

[Odd to Even]

0

+53.5

µsec

31.75

µs

4H

1H

end of vertical equalization pulse

VD input

prohibition time of

changing 33-pin signal

20

µs

20

µs

20

µs

20

µs

20

µs

20

µs

20

µs

20

µs

20

µs

20

µs

20

µs

20

µs

VD input

Driving Method and Operating Specification for Serial Interface Data

(1) Serial data transmission completion and start

A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial

transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the

serial transmission and waits for the following CLK and DATA inputs.

(2) Serial data transmission

The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-

byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for

acknowledge detection. (In writing state, SDATA outputs ‘L' under these two conditions ; 1) the coincidence of two

address data for the address data transmission, 2) the completion of 8-bit setting data transfer. In reading state, SDATA

outputs ‘L' with the address coincidence and SDATA becomes high-impedance for detecting acknowledge input from

the master (micro processor) after sending 8-bit setting data.) For address/data transmission, DATA must change while

CLK is 'L'. (The data change while CLK is 'H' or the simultaneous change of CLK and DATA, that will be a false

operation because of undistinguished condition from the completion / start of serial data transfer). After the beginning

of serial data transmission, the total number of data bytes that can be transferred are not limited.

(3) The byte format of data transmission (The sequence of data transmission)

a. The byte format during data writing to M65665CFP/SP are shown as follows.

In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards,

the internal register address (1 byte) and writing data (by 1 byte unit) are transferred successively. Several bytes of