SH7136 datasheet(18/1160 Pages) RENESAS

18 / 1160 page

Rev. 2.00 Sep. 10, 2008 Page xviii of xxvi

14.3.10 Bit Rate Register (SCBRR) .................................................................................. 553

14.4

Operation ........................................................................................................................... 564

14.4.1 Overview .............................................................................................................. 564

14.4.2 Operation in Asynchronous Mode ........................................................................ 566

14.4.3 Clock Synchronous Mode..................................................................................... 576

14.4.4 Multiprocessor Communication Function ............................................................ 585

14.4.5 Multiprocessor Serial Data Transmission ............................................................. 587

14.4.6 Multiprocessor Serial Data Reception .................................................................. 588

14.5

SCI Interrupt Sources and DTC ......................................................................................... 591

14.6

Serial Port Register (SCSPTR) and SCI Pins .................................................................... 592

14.7

Usage Notes ....................................................................................................................... 594

14.7.1 SCTDR Writing and TDRE Flag.......................................................................... 594

14.7.2 Multiple Receive Error Occurrence ...................................................................... 594

14.7.3 Break Detection and Processing ........................................................................... 595

14.7.4 Sending a Break Signal......................................................................................... 595

14.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 595

14.7.6 Note on Using DTC .............................................................................................. 597

14.7.7 Note on Using External Clock in Clock Synchronous Mode................................ 597

14.7.8 Module Standby Mode Setting ............................................................................. 597

Section 15 Synchronous Serial Communication Unit (SSU) ............................ 599

15.1

Features.............................................................................................................................. 599

15.2

Input/Output Pins...............................................................................................................601

15.3

Register Descriptions ......................................................................................................... 602

15.3.1 SS Control Register H (SSCRH) .......................................................................... 603

15.3.2 SS Control Register L (SSCRL) ........................................................................... 605

15.3.3 SS Mode Register (SSMR) ................................................................................... 606

15.3.4 SS Enable Register (SSER) .................................................................................. 607

15.3.5 SS Status Register (SSSR) .................................................................................... 609

15.3.6 SS Control Register 2 (SSCR2) ............................................................................ 612

15.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 613

15.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 614

15.3.9 SS Shift Register (SSTRSR)................................................................................. 615

15.4

Operation ........................................................................................................................... 616

15.4.1 Transfer Clock ...................................................................................................... 616

15.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 616

15.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 617

15.4.4 Communication Modes and Pin Functions ........................................................... 619

15.4.5 SSU Mode............................................................................................................. 621

15.4.6

SCS Pin Control and Conflict Error...................................................................... 630

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