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SH7149 Datasheet(PDF) 30 Page - Renesas Technology Corp |
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SH7149 Datasheet(HTML) 30 Page - Renesas Technology Corp |
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30 / 1022 page ![]() Rev. 3.00 May 17, 2007 Page xxx of xliv Figure 10.77 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) ..................................................................................... 397 Figure 10.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-Enabled Period...................................................................... 397 Figure 10.79 Example of Procedure for Specifying A/D Converter Start Request Delaying Function ........................................................................... 399 Figure 10.80 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation .... 400 Figure 10.81 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping............................................................. 401 Figure 10.82 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping............................................................. 402 Figure 10.83 Example of Synchronous Counter Start Setting Procedure................................... 403 Figure 10.84 (1) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:1)................................................ 404 Figure 10.84 (2) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:2)................................................ 405 Figure 10.84 (3) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:3)................................................ 405 Figure 10.84 (4) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:4)................................................ 406 Figure 10.85 Example of Procedure for Specifying MTU2S Counter Clearing by MTU2 Flag Setting Source............................................................................... 407 Figure 10.86 (1) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (1) ......................................................................... 408 Figure 10.86 (2) Example of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (2) ......................................................................... 408 Figure 10.87 Example of External Pulse Width Measurement Setting Procedure ..................... 409 Figure 10.88 Example of External Pulse Width Measurement (Measuring High Pulse Width).............................................................................. 409 Figure 10.89 Delay in Dead Time in Complementary PWM Operation .................................... 410 Figure 10.90 Example of Dead Time Compensation Setting Procedure .................................... 411 Figure 10.91 Example of Motor Control Circuit Configuration................................................. 411 Figure 10.92 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation .... 412 Figure 10.93 Count Timing in Internal Clock Operation (Channels 0 to 4) ............................... 418 Figure 10.94 Count Timing in Internal Clock Operation (Channel 5)........................................ 418 Figure 10.95 Count Timing in External Clock Operation (Channels 0 to 4) .............................. 418 Figure 10.96 Count Timing in External Clock Operation (Phase Counting Mode).................... 419 Figure 10.97 Output Compare Output Timing (Normal Mode/PWM Mode)............................. 419 Figure 10.98 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode).......................... 420 |
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