SH7201 datasheet(49/1196 Pages) RENESAS

Part #	SH7201

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

PDF	1196 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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49 / 1196 page

Section 2 CPU

Rev. 2.00 Sep. 07, 2007 Page 21 of 1164

REJ09B0321-0200

Bit

Bit Name

Initial

Value

R/W

Description

31 to 15

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

BO Bit

Indicates that a register bank has overflowed.

R/W

CS Bit

Indicates that, in CLIP instruction execution, the value

has exceeded the saturation upper-limit value or fallen

below the saturation lower-limit value.

12 to 10

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

—

R/W

—

R/W

M Bit

Q Bit

Used by the DIV0S, DIV0U, and DIV1 instructions.

7 to 4

I[3:0]

1111

R/W

Interrupt Mask Level

3, 2

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

—

R/W

S Bit

Specifies a saturation operation for a MAC instruction.

—

R/W

T Bit

True/false condition or carry/borrow bit

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