| Electronic Components Datasheet Search |
|
R8C2C Datasheet(PDF) 74 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R8C2C Datasheet(HTML) 74 Page - Renesas Technology Corp |
|
74 / 615 page ![]() R8C/2C Group, R8C/2D Group 7. Programmable I/O Ports Rev.2.00 Dec 05, 2007 Page 53 of 585 REJ09B0339-0200 7. Programmable I/O Ports There are 71 programmable Input/Output ports (I/O ports) P0 to P3, P4_3 to P4_5, P5 to P8 and P9_0 to P9_3. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used. Table 7.1 lists an Overview of Programmable I/O Ports. NOTES: 1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers PUR0, PUR1, and PUR2. 2. When the XIN clock oscillation circuit is not used, these ports can be used as the input-only ports. 7.1 Functions of Programmable I/O Ports The PDi_j (j = 0 to 7) bit in the PDi (i = 0 to 9) register controls I/O of the ports P0 to P3, P4_3 to P4_5, P5 to P8 and P9_0 to P9_3. The Pi register consists of a port latch to hold output data and a circuit to read pin states. Figures 7.1 to 7.11 show the Configurations of Programmable I/O Ports. Figure 7.12 shows the Configuration of I/O Pins. Table 7.2 lists the Functions of Programmable I/O Ports. Also, Figure 7.13 shows the PDi (i = 0 to 9) Registers. Figure 7.14 shows the Pi (i = 0 to 9) Registers, Figure 7.15 shows the P2DRR Register, Figure 7.16 shows the PMR Register, and Figure 7.17 shows Registers PUR0, PUR1, and PUR2. i = 0 to 9, j = 0 to 7 NOTE: 1. Nothing is assigned to bits PD4_0 to PD4_2, PD4_6, and PD4_7. Table 7.1 Overview of Programmable I/O Ports Ports I/O Type of Output I/O Setting Internal Pull-Up Resister P0 to P3, P5 to P8, P9_0 to P9_3 I/O CMOS3 State Set per bit Set every 4 bits(1) P4_3 I/O CMOS3 State Set per bit Set every bit(1) P4_4, P4_5 I/O CMOS3 State Set per bit Set every 2 bits(1) P4_6, P4_7(2) I (No output function) None None Table 7.2 Functions of Programmable I/O Ports Operation When Accessing Pi Register Value of PDi_j Bit in PDi Register(1) When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode) Reading Read pin input level Read the port latch Writing Write to the port latch Write to the port latch. The value written to the port latch is output from the pin. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |