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38K2 Datasheet(PDF) 73 Page - Renesas Technology Corp

Part # 38K2
Description  RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  358 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

38K2 Datasheet(HTML) 73 Page - Renesas Technology Corp

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FUNCTIONAL DESCRIPTION
Rev.2.00
Oct 15, 2006
page 54 of 130
38K2 Group
REJ09B0338-0200
HARDWARE
Fig. 77 Structure of EP10 control register 3
Fig. 78 Structure of EP10 interrupt source register
b7
b0
Control transfer completion
enable bit
Not used
CTENDE10
b7:b1
–
–
0
–
EP10 control register 3 (EP10CON3) [address 001C16]
0 : NAK transmission in the status stage
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (Valid in PID10 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
O
O
O
O
–: State remaining
Bit name
Bit symbol
At reset
Function
H/W
S/W
00
0
0
0
0
0
W
R
b7
b0
USB HUB/Endpoint 10 buffer
ready interrupt bit
USB HUB/Endpoint 10 control
transfer completion interrupt bit
USB HUB/Endpoint 10 status
stage transition interrupt bit
USB HUB/Endpoint 10 SETUP
buffer ready interrupt bit
USB HUB/Endpoint 10 error
interrupt bit
Not used
BRDY10
CTEND10
CTSTS10
BSRDY10
ERR10
b7:b5
0
0
0
0
0
–
0
0
0
0
0
–
EP10 interrupt source register (EP10REQ) [address 001D16]
Bit name
Bit symbol
At reset
Function
H/W
S/W
O
O
O
O
O
O
O
O
O
O
O
O
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when transition to status stage
occurs in CTENDE10 = “0” (control transfer completion
disabled) on USB HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when control transfer error occurs
on USB HUB/Endpoint 10.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
“0” is read when reading.
–: State remaining
000
W
R



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