38K2 datasheet(75/358 Pages) RENESAS

75 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 56 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

(6) Endpoint 11

Fig. 81 Structure of EP11 set register

Fig. 82 Structure of EP11 control register 1

Fig. 83 Structure of EP11 control register 2

Not used

Sequence toggle bit clear bit

Not used

Transfer direction bit

Not used

Transfer type bite

b2:b0

SQCL11

DIR11

TYP11

EP11 set register (EP11CFG) [address 001916]

–

Bit name

Bit symbol

At reset

Function

H/W

S/W

Write “0” when writing.

“0” is read when reading.

0 : Toggle bit clear disabled

1 : Writing “1” clears the toggle bit and DATA0 is used

as the next data PID.

“0” is always read when reading.

Write “0” when writing.

“0” is read when reading.

0 : IN transfer disabled

1 : IN (Data is transmitted to the host.)

Write “0” when writing.

“0” is read when reading.

0 : Transfer disabled

1 : Interrupt transfer

–: State remaining

Response PID bit

Not used

PID11

[1:0]

b7:b2

–

EP11 control register 1 (EP11CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (NAK, DATA0, DATA1)

1 X : STALL

Write “0” when writing.

“0” is read when reading.

–: State remaining

B0VAL11

b7:b1

–

EP11 control register 2 (EP11CON2) [address 001B16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

–: State remaining

Buffer 0 status bit

Not used

This bit set to “1” shows the transmitting data is in a set

state (SIE is possible to read).

Write “0” when writing.

“0” is read when reading.

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