38K2 datasheet(92/358 Pages) RENESAS

92 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 73 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

(1) External I/O Interface Part

The external I/O interface part consists of a command decoder

and an output selector. A command decoder generates the follow-

ing signals to each unit.

qCPU interface part

•CPU channel read (Cch_RD)

•CPU channel write (Cch_WR)

qInternal memory interface part

•Memory channel read (Mch_RD)

•Memory channel write (Mch_WR)

•Memory channel terminal count (Mch_TC)

qTransmit/receive data buffer part

•Buffer write (Buf_WR)

qExternal I/O interface part

•Status selection (stt_sel)

•Output enable (ExOE)

Access to the CPU channel can be controlled only by setup of

external signals.

Access to the memory channel can be controlled by the value of

the external I/O configuration register and the state (mRX_enb,

mTX_enb signals) of the internal memory interface part.

The output selector has the function which selects from the state

of CPU channel (TxB_RDY and RxD_RDY) and the state of

memory channel (Mch_req) as the signal assigned to P33/

ExINT pin and P40/ExDREQ/RxD pin.

(2) CPU Interface Part

The CPU interface part consists of the decoder/data selector of

the CPU channel, the CPU write register and CPU channel con-

troller

qDecoder/data selector of CPU channel

A write operation to the CPU register is performed by generating a

write signal for each register with an address decode signal and a

write signal.

A read operation from the CPU register is performed by generat-

ing an output enable signal of the internal data bus with an module

select signal and a read signal and generating a select signal for

each register with an address decode signal.

qCPU write register

There are three CPU write registers as follows:

•EXB interrupt source enable register

•Index register

•External I/O configuration register

The EXB interrupt source register is a read-only register.

A status signal of the CPU channel controller and a status signal

of the memory channel controller in the internal memory interface

part are generated.

qCPU channel controller

The CPU channel controller generates the following signals, using

bits 0 and 1 (RXB_ENB, TXB_ENB) of EXB interrupt source en-

able register.

•Memory channel transmitting buffer control signal (MRD_sel),

generated in the internal memory interface part

•CPU channel command signal (Cch_RD, Cch_WR), generated

in the external I/O interface part

•Signals RxB_RDY/RxB_full and TxB_RDY/TxB_empty, gener-

ated with read/write signals from the CPU channel

38K2 Datasheet(PDF) 92 Page - Renesas Technology Corp

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