HD6432351 datasheet(1012/1025 Pages) RENESAS

1012 / 1025 page

Appendix D Pin States

Rev. 3.00 Sep 15, 2006 page 978 of 988

REJ09B0330-0300

Port Name

Pin Name

MCU

Operating

Mode

Power-

Reset

Manual

Reset

Hardware

Standby

Mode

Software

Standby

Mode

Bus

Release

State

Program

Execution

State

Sleep Mode

PF2/LCAS/

WAIT/

BREQO

1, 2, 4 to 6

[BREQOE +

WAITE +

LCASE = 0]

kept

[BREQOE =

BREQO

[WAITE = 1]

[LCASE = 1]

[BREQOE +

WAITE +

LCASE = 0]

kept

[BREQOE = 1]

kept

[WAITE = 1]

[LCASE = 1,

OPE = 0]

[LCASE = 1,

OPE = 1]

LCAS

[BREQOE +

WAITE +

LCASE = 0]

kept

[BREQOE = 1]

BREQO

[WAITE = 1]

[LCASE = 1]

[BREQOE +

WAITE +

LCASE= 0]

I/O port

[BREQOE =

BREQO

[WAITE = 1]

WAIT

[LCASE = 1]

LCAS

3, 7

kept

I/O port

PF1/BACK

1, 2, 4 to 6

[BRLE = 0]

kept

[BRLE = 1]

BACK

[BRLE = 0]

kept

[BRLE = 1]

[BRLE = 0]

I/O port

[BRLE = 1]

BACK

3, 7

kept

I/O port

PF0/BREQ 1, 2, 4 to 6

[BRLE = 0]

kept

[BRLE = 1]

BREQ

[BRLE = 0]

kept

[BRLE = 1]

[BRLE = 0]

I/O port

[BRLE = 1]

BREQ

3, 7

kept

I/O port

PG4/CS0

1, 4, 5

2, 6

[DDR = 0]

[DDR = 1]

[DDR · OPE = 0]

[DDR · OPE = 1]

[DDR = 0]

Input port

[DDR = 1]

CS0

3, 7

kept

I/O port

1 to 3, 7

kept

I/O port

PG3/CS1

PG2/CS2

PG1/CS3

4 to 6

[DDR = 0]

[DDR = 1]

[DDR · OPE = 0]

[DDR · OPE = 1]

[DDR = 0]

Input port

[DDR = 1]

CS1 to CS3

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