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HD6432351 Datasheet(PDF) 1016 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 1016 Page - Renesas Technology Corp |
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1016 / 1025 page ![]() Appendix D Pin States Rev. 3.00 Sep 15, 2006 page 982 of 988 REJ09B0330-0300 Port Name Pin Name MCU Operating Mode Power- On Reset Manual Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode PG0/CAS 1 T kept T kept kept I/O port 4 to 6 T [DRAME = 0] kept [DRAME = 1] H* T [DRAME = 0] kept [OPE = 0] T [DRAME · OPE= 1] CAS T [DRAME = 0] Input port [DRAME = 1] CAS Legend: H : High level L : Low level T : High impedance kept : Input port becomes high-impedance, output port retains state DDR : Data direction register OPE : Output port enable WAITE : Wait input enable BRLE : Bus release enable BREQOE : BREQO pin enable DRAME : DRAM space setting LCASE : DRAM space setting, CW2 = LCASS = 0 Note: * Indicates the state after completion of the executing bus cycle. |
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