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HD6432351 Datasheet(PDF) 198 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 198 Page - Renesas Technology Corp |
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198 / 1025 page  Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 164 of 988 REJ09B0330-0300 6.5.6 Basic Timing Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle. The 4 states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle), and two Tc (column address output cycle) states, Tc1 and Tc2. Tp φ CSn (RAS) Read Write CAS, LCAS HWR, LWR D15 to D0 HWR, LWR D15 to D0 A23 to A0 Tr Tc1 Tc2 row column ( UWE, LWE) ( UWE, LWE) Note: n = 2 to 5 Figure 6.15 Basic Access Timing (2-WE System) |
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