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HD6432351 Datasheet(PDF) 200 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 200 Page - Renesas Technology Corp |
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200 / 1025 page  Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 166 of 988 REJ09B0330-0300 6.5.8 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. • Program Wait Insertion When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings of WCRH and WCRL. • Pin Wait Insertion When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figure 6.17 shows an example of wait state insertion timing. |
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