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HD6432351 Datasheet(PDF) 203 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 203 Page - Renesas Technology Corp |
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203 / 1025 page  Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 169 of 988 REJ09B0330-0300 H8S/2350 (Address shift size set to 9 bits) CS (RAS) 2-CAS type 4-Mbit DRAM 256-kbyte × 16-bit configuration 9-bit column address OE RAS CAS UCAS LCAS LCAS HWR (WE) WE A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 D15 to D0 Low address input: A8 to A0 Column address input: A8 to A0 Figure 6.19 Example of 2-CAS System Connection 6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit in MCR to 1. |
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