HD6432351 datasheet(206/1025 Pages) RENESAS

206 / 1025 page

Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 172 of 988

REJ09B0330-0300

RAS up mode: To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to

DRAM space is interrupted and another space is accessed, the

RAS signal goes high again. Burst

operation is only performed if DRAM space is continuous. Figure 6.22 shows an example of the

timing in RAS up mode.

In the case of burst ROM space access, the

RAS signal is not restored to the high level.

CSn (RAS)

CAS, LCAS

External space

access

A23 to A0

D15 to D0

Tc1

Tc2

Tc1

Tc2

DRAM access

Note: n = 2 to 5

Figure 6.22 Example of Operation Timing in RAS Up Mode

6.5.11

Refresh Control

The H8S/2350 Group is provided with a DRAM refresh control function. Either of two refreshing

methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing.

(1) CAS-before-RAS (CBR) Refreshing

To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0.

With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in

DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control

is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing is

HD6432351 Datasheet(PDF) 206 Page - Renesas Technology Corp