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HD6432351 Datasheet(PDF) 202 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 202 Page - Renesas Technology Corp |
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202 / 1025 page ![]() Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 168 of 988 REJ09B0330-0300 6.5.9 Byte Access Control When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6.18 shows the control timing in the 2-CAS system, and figure 6.19 shows an example 2-CAS system DRAM connection. When only DRAM with a ×8 configuration is connected, set the CW2 bit to 1 in MCR. Tp φ CSn (RAS) Byte control A23 to A0 Tr Tc1 Tc2 Row CAS LCAS HWR (WE) Column Note: n = 2 to 5 Figure 6.18 2-CAS System Control Timing (Upper Byte Write Access) |
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