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HD6432351 Datasheet(PDF) 207 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 207 Page - Renesas Technology Corp |
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207 / 1025 page  Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 173 of 988 REJ09B0330-0300 thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. Set a value in RTCOR and bits CKS2 to CKS0 that will meet the refreshing interval specification for the DRAM used. When bits CKS2 to CKS0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Do not clear the CMF flag when refresh control is being performed (RFSHE = 1). RTCNT operation is shown in figure 6.23, compare match timing in figure 6.24, and CBR refresh timings in figure 6.25. RTCOR H'00 Refresh request RTCNT Figure 6.23 RTCNT Operation RTCNT φ N RTCOR N H'00 Refresh request signal and CMF bit setting signal Figure 6.24 Compare Match Timing |
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